What is a clock data recovery circuit?

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According to the University of Toronto, "most integrated CDR circuits are based on using a Phase-Locked Loop (PLL) to self-align with the input when in lock and often a frequency-locked loop to help acquire lock." In other words, a Clock Data Recovery (CDR) Circut is used to re-sample data from other data imputs.

References:

University of Toronto: A 9-16Gb/s Clock and Data Recovery Circuit with Three-State Phase Detector

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